NSRRC Activity Report 2022

092 NSRRC ACTIVITY REPORT 2022 the DLLRF phase control, which primarily occurs because of the large phase jump. At this point, the tuner phase signal, which is defined as θ Pf − θ Pt + θ offset (normally 0°), reaches -15° and results in a misjudgment of the tuner- feedback loop. This phenomenon triggers interlocking after approximately 0.6 s, which is referred to as “Interlock,” at t 4 , which results in the stoppage of the feedback loop and causes the system to switch to the tuning mode for protection. Therefore, when the phase drift exceeds the integrated limit of the RF system and the DLLRF at t 2 , the DLLRF system exhibits a phase-lock fault. Although the phase drift slightly decreases and the gap voltage successively increases and decreases at t 3 , a misjudgment already occurs in advance at t 2 to stop the feedback loop. Thus, the RF system generates constant RF power, and the beam injection process fails thereafter. Phase Drift Compensation Loop After several tests on and modifications to the DLLRF system, 4 we concluded that the optimal solution to eliminate the large phase drifts observed during switching between the energy-saving and injection modes is to implement a phase drift compensation loop (PDCL) in the DLLRF system to reduce the phase compensation load of the PID controller. As shown in Fig. 3 , we relied on the principle of coordinate conversion to realize the PDCL logic. This logic is represented by the following three formulas: θ 0 = θ PID 0 – θ Pf 0 .................................................................... (1) θ 1 = θ PID 1 – θ Pf 1 .................................................................... (2) θ 2 = θ 1 – θ 0 .................................................................... (3) A coordinate rotation digital computer circuit was used to calculate the phases of the PID output, and P f was calculated and sent to a subtractor to obtain the phase difference, as indicated by Eqs. (1) and (2). After the initial phase difference (θ 0 ) was obtained at a normal I cc value, the instantaneous phase difference (θ 1 ) was calculated and subtracted from θ 0 to obtain the phase difference Fig. 1 : Phase variations of the DLLRF system ADC input and DAC output during injection mode switching. Fig. 2 : Transient data of ramp gap voltage failure of the RF system in the TPS booster ring. Fig. 3 : Structure of the PDCL logic.