0428同步年報-2021-全

Physics and Materials Science 017 Reference 1. B. G. Jang, G. Han, I. Park, D. Kim, Y. Y. Koh, Y. Kim, W. Kyung, H.-D. Kim, C.-M. Cheng, K.-D. Tsuei, K. D. Lee, N. Hur, J. H. Shim, C. Kim, G. Kotliar, Nat. Commun. 12 , 1208 (2021). Miniaturize Floating-Gate Transistors to Approach a Physical Limit On modulating the amount of electric-field-induced trapped electrons with an electrostatic gate potential, the demonstrated characteristics indicate that the engineering of an InSe interface has potential applications for nonvolatile memory. V an-der-Waals-bonded layered materials enable the isolation and subsequent construction of heterostructures with designer interfaces and without constraint of lattice matching. Such interface engineering provides a knob that controls the electron behaviors of the artificial structures by controlling the interactions between layers through variations in the symmetry, stacking angles and chemical composition. These layered structures have been incorporated into a nonvolatile memory cell to mimic the conventional setup in which a floating gate generates a long-lasting internal electric field. In the applications of transistor-type nonvolatile memory cells, stacks of graphene and insulating oxide have been incorporated to scale the floating gate (polysilicon/SiO 2 ), in which a long-lasting internal electric field continuously modulates the carrier concentration in the channel. In these heterostructures, charges are confined in the floating gate because of a difference in the barrier height of interface energy between the layered materials and the insulating oxides. Upon continuous device scaling, however, progress is hampered by diffraction-limited photolithography and nonscalable tunneling oxide thicknesses that contribute to, for example, back tunneling. Innovations in cell architecture, decreased fabrication complexity and new device materials are thus in high demand. Yi-Ying Lu (National Sun Yat-sen University), Chia-Hao Chen (NSRRC) and their teams proposed a new device concept that uses the van der Waals gating effect resulting from long-lived localized charges on the surface layer of InSe, which acts as an effective gate and which is separated by the van der Waals gap and generates a stable electron- storage effect in the underlying InSe channel. In contrast to a conventional flash memory cell in which charges are confined within potential wells formed by gate dielectric and semiconductor stacks, the charges in their structure are localized by trap sites generated by an indirect oxygen plasma treatment. Moreover, the channel current levels in InSe devices can be modulated on tuning the amounts of localized charge through the application of various back- gate voltages ( V G ), enabling multilevel data storage. To construct a back-gated field effect transistor (FET), two electrodes were deposited on both ends of InSe. The small bias current and bias voltage ( I DS − V DS ) measured at various V G values ranging from 0 to 70 V demonstrate a linear behavior that indicates an ohmic contact. To generate charge-trapping states (in-gap traps) on the surface layer without fully oxidizing it, the InSe FET device was then subjected to an indirect oxygen-plasma treatment. To verify the underlying physical mechanism of their proposed device, an operando investigation of the trapping and detrapping process on the top layer was performed using a scanning photoelectron microscope (SPEM) that combines the chemical and electronic sensitivities of X-ray photoelectron spectra (XPS) with a spatial resolution ~150 nm. Moreover, SPEM has the ability to reflect the local electrical potential surrounding the probed atom. This approach allowed to explore the role of surface oxides in device behavior through observation of the changes in binding energy for the device under working conditions. The operando SPEM measurement setup of their devices at TLS 09A1 beamline is illustrated in Fig. 1(a) (see next page). The device was scanned using a focused X-ray beam with spot size ~100 nm in ultrahigh vacuum conditions. To enable operando SPEM measurements during device operation, both source and drain electrodes were grounded; the gate electrode was subjected to a power bias. To verify the van der Waals gating effect, they performed operando SPEM measurements at the oxygen plasma- treated channel. Upon application of a V G 50 V, all signals moved to lower energies. To verify the trapped charge- induced core-level shifts, the In 4 d and Se 3 d binding energies are expressed relative to the In 4 d 5/2 and Se 3 d 5/2 signals, respectively. The relative energy difference between